1. Field of the Invention
The present invention relates to techniques for communicating between integrated circuit chips. More specifically, the present invention relates to an electrical-to-optical and optical-to-electrical transceiver chip to facilitate high-speed signaling between integrated circuit chips using optical coupling.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, including tens of millions of transistors, onto a single semiconductor chip. Integrating such large-scale systems onto a single semiconductor chip increases the speed at which such systems can operate, because signals between system components do not have to cross chip boundaries, and are not subject to lengthy chip-to-chip propagation delays. Moreover, integrating large-scale systems onto a single semiconductor chip significantly reduces production costs, because fewer semiconductor chips are required to perform a given computational task.
However, these semiconductor chips still need to communicate with other chips, and unfortunately, these advances in semiconductor technology have not been matched by corresponding advances in inter-chip communication technology. Semiconductor chips, are typically integrated into a printed circuit board which contains multiple layers of signal lines for inter-chip communication. However, a semiconductor chip typically contains about 100 times to 1000 times more signal lines than a printed circuit board. Consequently, only a tiny fraction of the signal lines on a semiconductor chip can be routed across the printed circuit board to other chips. This problem is creating a bottleneck that is expected to worsen as semiconductor integration densities continue to increase.
To overcome this communication bottleneck, researchers have recently developed an alternative technique, known as “Proximity Communication,” to communicate between semiconductor chips. Proximity Communication can be implemented by integrating arrays of capacitive transmitters and receivers onto active surfaces of integrated circuit (IC) chips to facilitate inter-chip communication. If a first chip is situated face-to-face with a second chip so that transmitter regions on the first chip are capacitively coupled with receiver regions on the second chip, it is possible to transmit signals directly from the first chip to the second chip without having to route the signal through intervening signal lines within a printed circuit board. The advantage of such an arrangement is that a large number electronic terminals on one chip can each communicate with corresponding electronic terminals on the other chip.
Proximity Communication makes it possible to communicate with an extremely large bandwidth per unit area. For example, the size and center-to-center pitch of Proximity Communication terminals, in an exemplary implementation, can be 20 microns and 30 microns, respectively. Moreover, under Proximity Communication, signals travel in the direction normal to the surface of the chip. Therefore, Proximity Communication allows communication to take place across a fully populated two-dimensional array of terminals, with many rows and many columns.
For comparison purposes, the size and pitch of a typical wire bond terminal may be 100 microns on a side with a pitch of 150 microns from the center of one terminal to the neighboring terminal. Furthermore, wire bonds are typically limited to a few rows. Hence, wire bonds generally cannot be used to provide a large fully populated two-dimensional array of terminals. Also, wire bonds are permanent, and do not permit rematabilty of connectors. (Note that term “rematability” refers to the ability to connect, disconnect, and reconnect terminals under field conditions.)
A significant limitation for conventional electrical interconnects is that they are designed either for moderate density (e.g. wire-bonds, or BGA) or for remateability (i.e. connectors), but not simultaneously for both. For instance, multiple solutions exist for remateable connections at the printed circuit board level. However, these connections have low-density and support only moderate bandwidth per connection. A high-density or even a moderate density connector that may be detachably connected to an individual IC chip does not exist.
Even if the problem of transporting data across chip boundaries at high bandwidth can be solved, the data must then be transported between chips at high bandwidth. This can be accomplished through optical communication techniques. Optical communication techniques have played a vital role in global, inter-state, metro, campus, intra-building, and central-office applications. However, to be of high utility within computer systems (i.e. “inside the box”), major improvements in I/O bandwidth-density are needed.
Optical interconnects have had significant penetration in board-to-board, rack-to-rack, and box-to-box interconnect applications. In these applications, optical transceivers with an aggregate capacity of 10 gigabits per second to 40 gigabits per second are the state of the art today. Typically, each transceiver provides 1, 4, or 12 separate channels arranged in one-dimensional 1×12 arrays. Optical transceivers based on two-dimensional arrays of optical lasers and optical detectors can potentially provide bandwidth in excess of 100 Gigabit per second.
For the foreseeable future, electrical ICs will be responsible for processing information. Therefore, any optically interconnected system will involve electrical-to-optical and optical-to-electrical conversion operations.
These conversion operations presently cause a number of electrical bottlenecks. The first electrical bottleneck appears between the optoelectronic driver and receiver circuits, and the photonic devices themselves. This bottleneck can be mitigated by integrating photonics onto IC chips and by creating optical modulators in silicon
A second electrical bottleneck appears in the data transport from the rest of the system (processors, memory, switching, control, etc) to the input of the optical transceiver. This bottleneck is more difficult to solve, due to a lack of very high-speed bus standards among processor vendors, and because there is no credible thermal or packaging solution that allows high-density optical technology to be combined with silicon processors. Furthermore, there are currently no accepted electrical interconnect solutions for aggregate off-chip bandwidth beyond 1-2 Tbps. Note that conventional technologies, such as wire-bonding, cannot scale to this bandwidth capacity.
Therefore, there is presently a need for improved communication techniques to provide additional bandwidth between electrical components and optical interconnects.